Lateral MOSFETS are susceptible to avalanche breakdown when reverse biased. Avalanche breakdown results in heating of the area around the breakdown path, and the ability to absorb the heat without damaging the MOSFET depends on the magnitude of the heat generated and the location of the avalanche breakdown path. If the breakdown current is highest at the upper surface of the MOSFET in the channel region next to the gate oxide, the gate oxide, which does not have good heat conductivity, may be damaged making the MOSFET unusable. Secondly, high avalanche current in the channel region may forward bias the well-to-source PN junction turning on a parasitic bipolar transistor inherent in the MOSFET design and putting the MOSFET into a latchup condition, further damaging the MOSFET.
As a result, areas away from the channel have been designed to go into avalanche before the channel region near the gate oxide. These areas limit or clamp the avalanche breakdown voltage to a voltage that is less than the reverse bias voltage needed to cause avalanche breakdown in the channel region. These areas are located in the bulk semiconductor material which has better heat tolerance and heat dissipation properties than the channel region.
Because all of the processing operations for forming a MOSFET are subject to inherent variations, the variations in the clamping voltage of the device must be compensated for by setting the nominal avalanche breakdown voltage in the channel region high enough so that lowest variation of the breakdown voltage in the channel is always greater than the highest variation in the breakdown voltage in the avalanche clamping voltage region. The avalanche breakdown voltage in the channel is determined by the dopant concentrations of the channel region and the drain region near the channel. A lower dopant concentration provides a higher avalanche breakdown voltage, but also increases the on resistance of the MOSFET. If the variations in the clamping voltage can be tightly controlled, the dopant levels in the drain region near the channel can be increased and the specified on resistance of the MOSFET can be lowered compared to MOSFETs without tight variations in the clamping voltages.